1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a full adder for implementing a carry logic block and a sum logic block with static and dynamic logics, respectively, using an NMOS transistor.
2. Discussion of Related Art
Generally speaking, a full adder is an adder that receives input signals and outputs two outputs, SUM and CARRY. In case of three-bit full adder, the sum and carry for input signals A, B and C can be expressed as the following logic functions.
SUM=A'B'C'+A'BC'+AB'C'+ABC PA1 CARRY=AB+AC+BC PA1 SUM'=CARRY'(A+B+C)+ABC PA1 CARRY'={AB+C(A+B)}'
FIG. 1 shows a conventional full adder using a CMOS transistor. This adder using CMOS transistor runs in negative logic so that the logic functions of SUM and CARRY should be implemented in the negative logic.
In FIG. 1 the conventional full adder is made up with first. to fourth logic blocks 11-14. The first logic block 11 receives three inputs A, B and C and implements inverted carry CARRY'={AB+C(A+B)}'. The second logic block 12 inverts the inverted carry CARRY' outputted from the first logic block 11 to thereby output carry CARRY. The third logic block 13 receives the inverted carry output CARRY' outputted from the first logic block 11, and three inputs A, B and C, to thereby implement inverted sum SUM'=CARRY'(A+B+C)+ABC. The fourth logic block 14 inverts the inverted sum SUM' outputted from the third logic block 13 to thereby output sum SUM.
The logic circuit of the full adder using CMOS transistor is expected to reduce the power consumption, but reduces the processing speed and increases the area of chip because it requires three-stage CMOS logic circuit in order to implement the full adder logic block.
Referring to FIG. 2, a full adder using complementary pass transistor logic (CPL) produces sum SUM and carry CARRY according to the exclusive-ORed signal of two inputs A and B and other input signal C.
If the first and second input signals A and B have different levels, the exclusive-ORed signal A.sym.B becomes HIGH so that transmission gates 23 and 25 are turned on and transmission gates 22 and 24 are turned off. As the sum SUM, third input signal C is output after being inverted, and as the carry CARRY, the third. input signal C is output as it as.
If the first and second input signals A and B have the same level, exclusive-ORed signal A.sym.B becomes LOW so that transmission gates 23 and 25 are turned off and transmission gates 22 and 24 are turned on. As the sum SUM, third input signal C is outputted as it is, and as the carry CARRY, the second input signal B is outputted as it is. The operation of the full adder using CPL is shown in table 1.
TABLE 1 ______________________________________ A B C B' A.sym.B 22 23 24 25 SUM CARRY ______________________________________ 0 0 0 1 0(B) ON OFF ON OFF 0(C) 0(B) 0 0 1 1 0(B) ON OFF ON OFF 1(C) 0(B) 0 1 0 0 1(B) OFF ON OFF ON 1(C') 0(C) 0 1 1 0 1(B) OFF ON OFF ON 0(C') 1(C) 1 0 0 1 1(B) OFF ON OFF ON 1(C') 0(C) 1 0 1 1 1(B) OFF ON OFF ON 0(C') 1(C) 1 1 0 0 0(B) ON OFF ON OFF 0(C) 1(B) 1 1 1 0 0(B) ON OFF ON OFF 1(C) 1(B) ______________________________________
Here, "1" represents the HIGH level signal, and "0" does the LOW level signal.
The full adder using CPL performs the full adding through the transmission gates results in a fast performance speed but there are drawbacks the overall power consumption and the area of chip are increased.
Referring to FIG. 3, like the full adder using CMOS transistor shown in FIG. 1, a full adder using pseudo-NMOS transistor includes first to fourth logic blocks 31-34 for outputting sum SUM and carry CARRY, having the same operation. The difference is that gate-grounded PMOS transistors MP31-MP34 as load are connected between the power terminal VDD and the output stages of the logic blocks. The full adder using pseudo-NMOS transistor can decrease the area of chip but also reduces the processing speed and increases the power consumption.
Referring to FIG. 4, like the full adder using CMOS transistor shown in FIG. 1, a full adder using quasi-domino logic has four logic blocks 41-44 for outputting sum SUM and carry CARRY. The third logic block 43 for outputting sum SUM is made with a dynamic logic circuit, the first logic block for outputting carry CARRY being with a quasi-dynamic logic circuit.
The first logic block 41 of the full adder using quasi-domino logic is designed to output inverted carry CARRY' at the output node NODE1, having a discharging portion with NMOS transistors MN11 and MN12 that perform discharging according to inverted clock CLKB. For instance, if the inverted clock CLKB is HIGH, NMOS transistor MN11 is turned on so that a current path is formed between output node NODE1 and ground VSS. In this state the first logic block 21 performs discharging, and node NODE1 becomes LOW.
Meanwhile, if inverted clock CLKB is LOW, NMOS transistor MN11 is turned off so that the inverted carry CARRY' at node NODE1 is determined according to three input signals A, B and C. Here, inverted carry CARRY' at node NODE1 is shown in table 2.
TABLE 2 ______________________________________ A B C MP13 MP12 MP11 MP14 MP15 NODE1 ______________________________________ 0 0 0 ON ON ON ON ON 1 0 0 1 OFF ON ON ON ON 1 0 1 0 ON OFF ON ON OFF 1 0 1 1 OFF OFF ON ON OFF 0 1 0 0 ON ON OFF OFF ON 1 1 0 1 OFF ON OFF OFF ON 0 1 1 0 ON OFF OFF OFF OFF 0 1 1 1 OFF OFF OFF OFF OFF 0 ______________________________________
In table 2, if two input signals A and B, A and C, or B and C are LOW at the same time, and only if three inputs A, B and C are LOW at the same time, the inverted carry CARRY' at node NODE1 becomes HIGH. Therefore, it is noted that the first logic block 41 performs CARRY'={AB+C(A+B)}'.
The inverted carry CARRY' of first logic block 41 is applied to the second logic block 42, a dynamic inverter logic logic circuit. The second logic block 42 inverts the inverted carry CARRY' outputted from first logic block 41 according to clock CLK that is HIGH, to thereby output carry CARRY.
The third logic block 43 is a quasi-dynamic logic circuit that performs SUM'={CARRY'(A+B+C)+ABC}'. As the precharging portion for precharging node NODE2, third logic block 43 comprises PMOS transistor MP31. In other words, if clock CLK is LOW, PMOS transistor MP31 is turned on so that node NODE2 is precharged in the HIGH state. If clock CLK is HIGH, PMOS transistor MP31 is turned off so that the inverted sum SUM' at node NODE2 is determined according to inputs A, B and C as shown in table 3.
TABLE 3 __________________________________________________________________________ A B C NODE1 MN35 MN33 MN31 MN32 MN34 MN36 MN37 NODE2 __________________________________________________________________________ 0 0 0 1 OFF OFF OFF OFF OFF OFF ON 1 0 0 1 1 ON OFF OFF OFF OFF ON ON 0 0 1 0 1 OFF ON OFF OFF ON OFF ON 0 0 1 1 0 ON ON OFF OFF ON ON OFF 1 1 0 0 1 OFF OFF ON ON OFF OFF ON 0 1 0 1 0 ON OFF ON ON OFF ON OFF 1 1 1 0 0 OFF ON ON ON ON OFF OFF 1 1 1 1 0 ON ON ON ON ON ON OFF 0 __________________________________________________________________________
In table 3, if inverted carry CARRY' at node NODEl is HIGH, input A, B or C is HIGH, and three inputs A, B and C are HIGH at the same time, node NODE2 becomes LOW. Therefore, third logic block 43 outputs inverted sum SUM' at node NODE2 according to clock CLK that is HIGH.
Like the second logic block 42, the fourth logic block 44 is a dynamic inverter logic circuit that inverts the inverted sum SUM' output from third logic block 43 according to HIGH clock CLK to thereby output sum SUM.
The quasi-domino full adder logic circuit increases the overall area of chip because the first logic block 41 outputting inverted carry CARRY' is implanted with a PMOS transistor. In addition, the width of voltage swing at nodes NODEI and NODE2 increases to reduces the processing speed in turn because the pull-up transistor is made with PMOS transistor.